Ever since people have identified it as a roadblock in Nvidia's AI chip production and thus its stock price.

TSMC has accelerated construction on several advanced packaging fabs across Taiwan to unblock this plug.

At the same time, they and the rest of the industry are moving forward on an interesting technology that not only panels.

Chips on panels.

In this video, we're going to talk about this new thing on the semiconductor horizon.

The chiplet-slash-tile approach is a cost-saving one.

We fabricate chiplets using the appropriate node and then integrate them all together inside a single package.

This is in contrast to a monolithic chip where a node makes the whole chip all at once.

The advantage of chiplets is that only the most complicated part of the package needs to be made by the most advanced node, which suffers the lowest yields.

Not every part of the chip needs an N3E node.

Another advantage of chiplets has to do with design migration.

Thanks to the AI boom, we're seeing several chipmakers, Nvidia foremost, move to an annual refresh cycle.

Being able to update just the most value-added part of the package without redoing the whole thing is a nice perk.

Roughly speaking, the industry has two methods-slash-philosophies for integrating these chiplet pieces together. 2.5D and 3D integration.

And before we start, I do want to note that the semiconductor packaging industry's naming conventions are chaotic.

The standardization is not that great.

What follows are rough definitions.

Let us start with 3D.

We just stack these puppies vertically.

This can offer the smallest size package, fastest connections, and so on.

But 3D has issues like heat retention and failure analysis.

As in, we can't see into the package.

So the industry introduced what is called 2.5D integration.

This is where we package disparate parts of the system, digital logic, the memory input and output, side by side on top of a substrate.

Early on, 2.5D was seen as a mere layover on the path towards true 3D integration.

But that is no longer the case.

Today's high might, for example, 3D integrate the memory chips, big stacks of what we call high-bandwidth memory.

That HBM will then be integrated side by side with the chip's other portions using 2.5D.

TSMC has said that by 2027, you might see systems with 12 or more stacks of these little guys.

One major concern with the chiplet approach has been communication.

The whole system can only work as fast as its slowest component.

How are we going to have these different chiplets communicate with one another?

We can use layers of copper interconnects to redistribute signals horizontally across the system package.

We call this the redistribution layer or RDL and they are immensely valuable.

RDLs have another major use case.

If a chip die has many densely packed connections, often the case for smaller chips, the connections are too small to match up with the larger, solder balls through which the chip communicates with the outside world.

RDLs can help distribute or fan out these connections, matching size to size.

The ability to fan out was one of TSMC's breakthrough packaging offerings to Apple with their integrated fan out or info technology.

These RDL layers can either sit on top of, below, or be a part of what we call an interposer.

You can think of it as like a PCB and they do sort of serve similar purposes.

That interposer in turn sits on top of a substrate.

Traditionally, the substrate provides the package's mechanical backbone.

In other words, it keeps the delicate silicon die from bending.

The chip still has to communicate with the PCB below it.

So, this substrate and the interposer must also have through vias, which are vertical copper interconnects, running through them.

So good rule of thumb, RDLs are horizontal while through vias are vertical.

Since the packaging industry is chaos, we should not always expect the interposer and substrate to be distinct separate things.

Sometimes the interposer does substrate-like things, invalidating the need for a separate substrate.

It is all dependent on the product's spec and design.

Late last year, Intel announced glass quote unquote core substrate panels for use in advanced packaging solutions.

To repeat, the substrate helps keep the die mechanically stable.

Most often, it was made from a core panel of metal, ceramic, or organics.

The cores are then covered with layers of other stuff.

The first Intel CPUs had substrates of ceramic.

Then, in 1995, Intel led an industry change from ceramics to organics like epoxy resin, with glass fibers woven into them.

The new change that Intel is proposing here is to use substrate panel cores of pure glass.

This is because of glass's physical properties.

Glass offers better heat tolerances and a superflat surface which can support a denser network of interconnects and easier to inspect the package for issues.

This has been a major problem with these complicated packages.

How do you look into them?

Anyway, it was a brief announcement and so did not get much attention.

But Intel has long been, and still is, a trendsetter.

I give them full credit for kicking this off.

So TSMC and Samsung have in turn followed on.

Substrates are relatively simple structures.

Glass has a few tricky things, which we can talk more about later.

But it will probably work.

Can a glass panel, however, replace the far more complicated silicon interposer?

Today, the industry makes almost all of their interposers from silicon wafers, like the ones to make the silicon dye.

In many ways, silicon is a fine choice.

The technology is super mature and offers the best performance.

As in, it lets us produce the densest layers of interconnects.

The techniques have been around for decades now.

Silicon also lets us put devices like transistors right inside the interposer.

Such interposers are called active interposers.

One without devices and has just the interconnects is called, naturally, a passive interposer.

So that's the upsides.

What are the downsides?

One major issue is that using silicon is expensive and a bit wasteful.

It means making interposers from the same massive silicon crystals that we the Czochralski process where we slowly pull a crystal out of a melt.

Then after that, we must cut, polish, and prepare that crystal into wafers in a series of expensive steps.

This could potentially hurt yield, which is not ideal.

Not to mention, drilling through vias into silicon is a complicated process.

This is because the wires going through the vias are made from copper, and if we don't apply protective liners, then the copper diffuses into silicon.

It works, but it sometimes feels like overkill.

Another economics-related problem is that the silicon crystals are round and can only be about 200mm or 300mm wide, the silicon industry's standard wafer size.

This limits how many interposers you can cut out from a single silicon crystal.

The big NVIDIA Blackwell chips need big rectangular interposers and you can only get like four of them out of a single 300mm wafer.

Moreover, there is some wasted space.

Cut out a bunch of squares or rectangles out of a round wafer and you are left with some wasted silicon at the edges.

So if you can make interposers out of a rectangular panel, you get some major cost savings.

You can better utilize the space and in some cases, get up to 8x more usable panels, which cuts per panel cost.

The issue is figuring out what material we should make the panels out of.

Because there are always tradeoffs.

Since the mid-2010s, the industry has been investigating organic interposers.

Interestingly enough, actually finding out what these organics in the organic interposers are is a bit of a chore.

The best that I can do is that they are composed of multiple layers like how they make PCBs today.

At their core, you might use a material like bismaleamide triazine resin or BT epoxy, which is already used for circuit boards.

Another is FR-4 substrate, another epoxy resin with fiberglass woven into it.

FR-4 is particularly known for its resistance to flames.

The FR stands for flame retardant.

It's pretty tough and strong and holds up well in humidity.

Organic interposers are cheaper than silicon interposers, not just in financial cost but complexity cost as well.

They are easy to process.

You don't need particular steps.

And so on.

But organics have two major downsides.

First, the performance is worse.

The smallest possible width of the lines and the spacing between them is about 2 microns.

So we cannot achieve the same interconnect density as with silicon.

Second, there is a warpage problem.

Semiconductors get hot and managing those thermals gets far trickier with these packages.

When any substances get exposed to heat, their size changes.

That change is determined by a factor known as Coefficient of Thermal Expansion or CTE.

No relation to chronic traumatic encephalopathy, the brain disorder caused by repeated head trauma due to things like NFL tackles or studying advanced packaging terminologies.

Organic interposers are not as good as conducting away and dissipating heat as silicon ones are.

Thus you tend to get hotspots inside the package, which require intense computations to identify.

And what is the problem with the hotspots?

Well, the CTE of the organics are not matched up well with that of the silicon dye or the substrate.

So the hotspots make the organics warp, ruining the whole package.

Just like how organics came from the PCB industry, the microelectronics industry has long been familiar with glass panels.

We produce liquid crystal displays on top of them, layering on thin film transistors or TFTs on top of a precisely manufactured glass substrate.

The panels used for these displays have to be extremely well crafted.

They need to be very thin, maybe about 200 micrometers thick.

Yet at the same time, the panel has to be strong enough to resist falls.

Oh, and as always, it needs to be affordable.

Corning produces most of these glass panels.

In the 1960s, they invented and patented the fusion draw process, originally for making the windshields of cars.

The fusion draw is pretty crazy.

You put molten glass into a V-shaped trough and then overflow it.

The glass spills over both ends and then meet at the bottom of the V.

There they fuse, creating a sheet.

Amazing technology.

But with the LCD industry on the decline thanks to OLED's dominance, Corning has been doing R&D to see if their glass technologies can be applied to packaging.

Since 2010, teams at the 3D Systems Packaging Research Center at Georgia Tech have been investigating the possibility of using glass interposers for high performance computing.

To make one, you start with a special glass panel core.

We then drill into that core thousands of through-glass vias or TGVs.

These TGVs are then filled with copper.

And after that, we laminate RDLs and patterns onto both sides of the glass interposer core.

Glass is already used in a few applications like MEMS and RF, but high compute would be like going to the major leagues.

Glass offers many upsides.

One of the problems with the organic interposers was warpage.

While it can still be a concern if your glass panels are very large, glass is nice because we can better adjust its CTE via its composition to better match it to the silicon die and the substrate below.

Glass's major downside, however, might be quite familiar to you.

Cracking.

Just cutting the glass panel dies out of their big panels can be challenging.

We use a mechanical saw to do this, and early tests have noticed that it to appear.

The industry has taken to call these cracks seware after the Japanese phrase meaning splitting of the back.

Even the smallest cracks can propagate throughout the rest of the panel, basically ruining it.

Seware failures can happen either because of deep, sharp defects left behind by the cutting process, or because of tensile stresses from the various copper interconnect layers laminated onto its surfaces.

Japan's DISCO Corporation ran a few experiments and found a pretty nice method to avoid some seware failures, using a dicing blade made from diamond grit of a very specific size, and pulse lasers also did a fine job as well.

Moreover, to work as a glass interposer, the panel must accommodate maybe tens of thousands of TGVs without cracking.

This is a major obstacle.

The industry has investigated how to make these, from lasers to acids to just a straight up drill.

And what techniques should we employ here?

Do we drill straight through?

We call those through holes.

Or do we stop short of the surface and ground down the opposite surface to reveal the via?

That is a blind hole.

We have yet to find the right tool and technique for doing this at scale.

Such issues with panel warpage and cracking will open opportunities again in metrology.

There are already some intriguing companies in the space, several of whom are pivoting over from the declining LCD panel world.

So panel-level packaging has been around for a while.

The question is whether or not the technology is finally about to hit the big time.

Intel has kicked off the race for glass substrates and I on glass interposers as well behind the scenes.

But the rest of the industry is catching up.

It was news that TSMC spent about half a billion dollars to acquire an LCD panel fab in Tainan from Inolux.

They apparently intend to use it for advanced packaging purposes, which to me is panel-level packaging.

Side note, the Taiwanese LCD industry's slow decline is an interesting trend.

For a write-up, go check out the newsletter Tim Coulpin's Position.

He has done great analysis and reporting on this industry since before this channel even existed.

Anyway, that panel-level packaging was so prominently featured by TSMC, ASC, and the rest of the industry at Semicon 2024 is another hint that this stuff is coming along.

Some are even calling it inevitable.

The challenges are formidable, but I expect these to start coming along in the near future two to three years.